Xilinx中的"死代码"

我有一些我正在为一堂课写的VHDL代码.但是,综合工具将cell3,cell2和cell1识别为"死"代码,并且不会合成它.

我真的不知道是什么导致细胞3,2,1在合成中被去除; 我已经回顾了5次以上并且询问了几个不同的人,我找不到"为什么".

不寻找解决方案,只是指向原因的指针.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity multiply is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;

           p : out  STD_LOGIC);

end multiply;

architecture Behavioral of multiply is

    component cell_a port(
                s: in std_logic;
                c: in std_logic;
                a: in std_logic;
                b: in std_logic;
                clk: in std_logic;

                c_out: out std_logic;
                s_out: out std_logic);
    end component;

    signal c_s_0: std_logic;    --loopback wire for cell 0 from carry to sum
    signal c_s_1: std_logic;
    signal c_s_2: std_logic;
    signal c_s_3: std_logic;

    signal xfer1_0: std_logic;  --wire between 1 and 0
    signal xfer2_1: std_logic;  --"     2 and 1
    signal xfer3_2: std_logic;      --"     3 and 2


begin

    cell3: cell_a port map(
                                    clk => clk, 
                                    s => c_s_3 , c => '0',   a => a(3), b => b,
                                    c_out => c_s_3, s_out => xfer3_2
                                    );

    cell2: cell_a port map(
                                    clk => clk, 
                                    s => c_s_2 , c => xfer3_2, a => a(2), b => b, 
                                    c_out => c_s_2, s_out => xfer2_1
                                    );

    cell1: cell_a port map(
                                    clk => clk, 
                                    s => c_s_1, c => xfer2_1, a => a(1), b => b, 
                                    c_out => c_s_1, s_out => xfer1_0
                                    );

    cell0: cell_a port map(
                                    clk => clk, 
                                    s => c_s_0 , c => xfer1_0, a => a(0), b => b, 
                                    c_out => c_s_0, s_out => p
                                    );
    process(clk)
    begin
        if(clk'event and clk = '1') then
            if(rst = '1') then
            --reset logic here. Magic happens and the circuit goes to all 0
            end if;
        end if;
    end process;
end Behavioral;

Zooba.. 8

所有我可以建议,没有看到代码的其余部分是你的cell_a的'c'输入未使用,这导致cell3/2/1的所有输出都未被使用(因此,死代码,因为它不会产生可观察的结果) .

cell0实例化,因为乘数的'p'输出是可观察的.

所有我可以建议,没有看到代码的其余部分是你的cell_a的'c'输入未使用,这导致cell3/2/1的所有输出都未被使用(因此,死代码,因为它不会产生可观察的结果) .

cell0实例化,因为乘数的'p'输出是可观察的.